Stop truncating ARM64 system register access to 32 bits

The generated stubs are mrs x0, <reg>; ret and msr <reg>, x0; ret, but the
prototypes were unsigned arm_mrs(unsigned) and
void arm_msr(unsigned, unsigned). AArch64 system registers are 64-bit, so
every read lost its upper half -- and on write, AAPCS64 leaves bits [63:32]
of x0 unspecified while the stub writes all 64, so uncontrolled data went
into a privileged system register.

Widen both to uint64_t values with a uint32_t instruction word.

Also document the ARM64 calling convention in native.inc, which said nothing
about it: the msr parameter is an assembled MRS instruction word, and the
read encoding is what gets validated in both directions.