[BugFix][ROCm] Lower vector Select conditions lane-wise (#2889)

#2843 fixed vectorized `T.Select` in the CUDA codegen but the equivalent handling
never landed for HIP, so on gfx942 a vector condition fell through to a scalar
ternary and failed to compile:

    error: value of type 'ushort4' (aka 'HIP_vector_type<unsigned short, 4>')
           is not contextually convertible to 'bool'

Lower vector Select conditions lane-wise instead, scalarizing the expression tree
per lane so branch loads stay inside the ternary rather than being materialized.
Also adds fp8/fp4 handling to PrintVecElemLoad/PrintVecElemStore, which the new
path exercises.

Verified on the gfx942 runner: 1910 passed, 1237 skipped, 0 failed. First fully
clean ROCm leg since CI was re-enabled in #2874.

Known follow-up: vector `builtin::reinterpret` is not scalarized before lane
extraction. A limitation of the new path rather than a regression, tracked
separately.