Enable the decode pipeline by default (#611)

#588 landed the one-step-ahead decode pipeline opt-in, with default-on
gated on a tighter contract: the cached re-entry path, the executor
gate, and more real-model results. The first two landed inside #588
itself: the pending-row coverage check and the positive uniproc check.
This PR flips the default now that the mileage exists.
`VLLM_METAL_DECODE_PIPELINE=0` stays as the kill switch back to the
fully synchronous path.

Kill-switch A/B on my M1 Ultra (`VLLM_METAL_MEMORY_FRACTION=0.5`, greedy
chat completions, decode tok/s):

| model | off | on |
|---|---:|---:|
| Qwen3.6-35B-A3B-4bit | 44.3 | 57.1 |
| Qwen3.8-27B-4bit  | 22.3 | 25.3 |
| gemma-4-26B-A4B-it-OptiQ-4bit | 46.9 | 53.5 |
| gemma-4-e2b-it-4bit | 56.6 | 84.2 |
| MiniCPM3-4B-4bit (MLA) | 37.7 | 39.8 |
| Qwen3-0.6B | 109.7 | 146.5 |

Signed-off-by: RickyChen / 陳昭儒 <ricky.chen@infinirc.com>