[Fix] Fix XQA V tile reading from wrong page when nbVItersPerXIter > 1 (#3022)

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## 📌 Description

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## Summary
Fix incorrect XQA attention results on architectures with
`cacheVTileSeqLen = 32` (SM120/SM121) when `head_dim = 256` and
`page_size < 64`.
## Bug
On SM120 with `head_dim=256` and `page_size` of 16 or 32, the XQA
`mha.cu` kernel produces incorrect attention outputs. All `page_size=64`
cases pass; all `page_size < 64` cases fail. The bug is independent of
dtype, `kv_layout`, `batch_size`, `window_left`, and other parameters.
SM90 and SM100 are unaffected.
## Root Cause
In `mha.cu`, the V tile page advancement logic (`loadVTilePart` lambda)
has two branches based on `xIterSeqStride` vs `tokensPerPage`. The
`else` branch (when `xIterSeqStride > tokensPerPage`) assumes
`nbVItersPerXIter == 1`, meaning each warp X tile (64 tokens) is covered
by a single V tile load. This assumption is violated under a specific
combination of compile-time constants:
- `cacheVTileSeqLen = 32` (SM120/SM121)
- `head_dim = 256` → `gemm1WarpsPerGrp = 4`, `gemm1NbWarpGrps = 1`
- → `cacheVTileSeqStride = 32 × 1 = 32 < warpTile.x = 64`
- → **`nbVItersPerXIter = 2`**
With `nbVItersPerXIter = 2`, each warp X tile requires two V iterations
(vIter=0 covering tokens [0, 32) and vIter=1 covering tokens [32, 64)).
When `page_size < 64`, these two V iterations land on different pages.
However, `loadPages()` was only called after the last V iteration
(`vIter == nbVItersPerXIter - 1`), leaving the page index stale for
vIter=1 — it reads KV cache data from the wrong page.
On SM90/SM100 (`cacheVTileSeqLen = 64`), `cacheVTileSeqStride = 64` and
`nbVItersPerXIter = 1`, so the bug never triggers. On SM120 with
`head_dim = 128`, `gemm1NbWarpGrps = 2` makes `cacheVTileSeqStride =
64`, also avoiding the issue.
## Fix
Replace the single page advancement at the end of each X iteration with
per-V-iteration page advancement:
- **Intermediate V iteration** (`vIter < nbVItersPerXIter - 1`): advance
`idxPageBeg` by `step_per_viter = cacheVTileSeqStride / tokensPerPage`
and reload pages.
- **Last V iteration, last beam** (`isLastVIter && isLastBeam`): advance
with CTA-tile boundary wrapping (multi-block mode), same as original but
using `step_per_viter`.
- **Last V iteration, not last beam** (`isLastVIter && !isLastBeam`):
reset `idxPageBeg` backward so the next beam restarts from `vIter=0`'s
page position.
When `nbVItersPerXIter == 1`, only the first branch fires and the
behavior is identical to the original code — no performance or
correctness impact on existing working paths.
## Test Plan
- [x] `test_trtllm_batch_decode` with `backend=xqa`, `head_dim=256`, all
page sizes (16, 32, 64) on SM120
- [x] `test_trtllm_batch_decode` with `backend=xqa`, `head_dim=128`, all
page sizes on SM120 (regression check)
- [x] `test_trtllm_batch_decode` with `backend=xqa`, `head_dim=256`, all
page sizes on SM90 (regression check)

## 🔍 Related Issues

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<!-- This is an auto-generated comment: release notes by coderabbit.ai
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## Summary by CodeRabbit

* **Bug Fixes**
* Improved attention page-loading to correctly handle multi-iteration
stride scenarios, including proper advance, rewind and reload behavior
across iteration and beam boundaries for more reliable caching.

* **Tests**
* Re-enabled tests for configurations with head_dim == 256 that were
previously skipped to verify multi-iteration page-loading.
<!-- end of auto-generated comment: release notes by coderabbit.ai -->

Signed-off-by: Qidi Sang <200703406+qsang-nv@users.noreply.github.com>